Marvell Unveils Second-generation Structera X, Industry-first Six-channel CXL 3.2 Memory Expanders for AI Inference

What Marvell announced

Marvell released the Structera X 3406 and Structera X 3506 CXL memory expanders, described as second-generation devices built for cloud, enterprise and AI infrastructure providers. The company states these controllers add six DDR4/DDR5 channels and PCIe Gen 6 connectivity, and that they extend the existing Structera X 2404 and 2504 architecture already shipping to hyperscalers. Marvell positions the products for workloads it characterizes as memory bound, such as LLM serving and deep learning recommendation models (DLRM). (Issuer claim: Marvell press release.)

Sources: S1

Key technical claims from the release

Marvell describes the new controllers as offering industry-first six-channel CXL memory expansion, four-host connectivity and higher compression throughput. The company states the devices deliver increased memory capacity per controller, multi-host sharing with up to 256GB/s PCIe6.0 x16 of host bandwidth, up to 250GB/s compression/decompression throughput, and a suite of RAS and security features including post-quantum cryptography and AES-256 memory encryption. These are presented as product specifications and architectural features in Marvell’s announcement.

Sources: S1

Performance and use-case claims

Marvell reports workload-specific improvements: for DLRM workloads, up to 2x higher queries per second and 2–3x more effective embedding-table capacity per controller; for LLM serving, up to 40–50% faster time to first token (TTFT) at equivalent context length or up to 2x longer supportable context windows at equivalent latency versus the prior generation. The release also highlights multi-host sharing and compression as mechanisms to increase effective capacity and memory utilization across AI clusters.

Sources: S1

Availability and ecosystem notes

Marvell says the Structera X 3406 and 3506 are expected to sample in Q1 2027 and that the company will demo the products at the 2026 OCP Global Summit. The release cites partner endorsements from several CPU and memory vendors and refers to an existing ecosystem and software stack that supports the new controllers.

Sources: S1

Inference (why this could matter)

If the technical claims are validated in systems, increased channel count, multi-host sharing, and higher compression throughput could alter how memory capacity is provisioned for AI inference workloads by increasing nominal and effective memory per controller and by enabling sharing across hosts. That could be relevant to hyperscalers and large AI deployments seeking higher memory utilization and lower TTFT for LLM serving. This paragraph is an editorial inference based on the product claims in the release.

Sources: S1

What remains uncertain

• All performance and capacity numbers are issuer-provided claims from the Marvell press release and are not independently verified in this draft.
• Statements framed as "expected" (sampling timeline) are forward-looking and subject to change; the release notes forward-looking statement risks without independent corroboration.
• Workload impact metrics (for DLRM and LLMs) depend on unspecified benchmark conditions, model configurations, and deployment contexts that are not detailed in the release.